The present invention relates to a digital image processor capable of displaying, on a screen, a video signal and a character and/or graphic pattern using one memory.
This application is based on Japanese Patent Application No. 08-92514, filed Apr. 15, 1996, the content of which is incorporated herein by reference.
As has been known in recent years, raising of the integration degree and operation speed of digital LSI (Large-Scale Integrated) circuits, particularly, memory access rate, enlargement of the memory capacity and reduction in the cost have caused digital signal processes of video signals to be performed widely. The digital signal processing method has been widely employed also in the personal use television receivers. The main reason for this is that use of the digital signal processing method has realized a variety of additional values which cannot be realized by the analog system.
As a method of displaying characters and figures (for displaying the channel number, the sound volume level and the like) adapted to the television receiver of the foregoing type using the digital image processing apparatus, there are available a method structured as shown in FIG. 1A such that characters and figures are reproduced from pattern data corresponding to each pixel of the characters and figures; and a method structured as shown in FIG. 1B such that characters and figures are reproduced from codes corresponding to the characters and figures. Referring to FIG. 1A, pattern data in a hatched line portion of interest is formed into a pulse signal including pulses corresponding to solid pixels. In FIG. 1B, the overall portion of one character "A" corresponds to a code (for example, 00100000001).
Since the method shown in FIG. 1A has configured such that each pixel has data, precise expression can be performed and satisfactory degree of freedom can be obtained in display. However, there arises a problem in that a large capacity memory is required. Thus, the method shown in FIG. 1B has been used widely in recent years.
An example of display performed by the method shown in FIG. 1B is shown in FIG. 2. Video signal S1 is supplied to an input terminal 11. The video signal S1 supplied to the input terminal 11 is supplied to an input terminal of a memory 12 and one of input terminals of a video processor 13. The memory 12 stores the video signal S1 for one frame. The memory 12 reads a video signal S2 for one frame, preceding to the video signal S1 supplied through the input terminal 11 by one frame so as to output the video signal S2 to another input terminal of the video processor 13. The video processor 13 performs, for example, a motion adapted 3D Y/C separation process. The video processor 13 subjects the input video signal S1 and the video signal S2 output from the memory 12 to a video process so as to output a video signal S3 subjected to the video process to one of input terminals of a selector 14. Pattern data is supplied to another input terminal of the selector 14.
Pattern data is read out from a code generator 22 in response to a timing signal S4 generated from a timing generator 16. The timing generator 16 generates appropriate timing signals S4, S5 and S7 in response to horizontal and vertical synchronizing signals H and V supplied to a terminal 17 in order to cause a pattern to be displayed at a desired position in one image. A signal S11 output from the code generator 22 and including code data is supplied to a display memory 23. Code data in the display memory 23 is read in response to the timing signal S5 generated by the timing generator 16. Thus-read code data is supplied to a character ROM 24 so that a character and/or figure pattern corresponding to the code is generated. The output from the character ROM 24 is supplied to a display controller 19. The display controller 19 subjects supplied pattern data to the Y/C separation process and the like so as to output Y, I and Q signals (or R, G and B signals) as signal S8. The output signal S8 from the display controller 19 is supplied to another input terminal of the selector 14.
The selector 14 switches the signal S8 supplied from the display controller 19 and including pattern data and the video signal S3 supplied from the video processor 13 in response to the timing signal S7 output from the timing generator 16 so that the characters and figures are displayed at desired positions in one image. Output signal S9 from the selector 14 is supplied to an RGB signal converter 20 so as to be subjected to a conversion process. The RGB signal converter 20 subjects the supplied signal S9 to an R, G and B signals process so as to generate red, green and blue signals R, G and B so as to output the R, G and B signals to a monitor (not shown) through a terminal 21. If the display controller 19 outputs the R, G and B signals, the RGB signal converter 20 can be omitted.
As a matter of course, the above-mentioned display method involves the degree of precision of displayed characters and figures being different based on the quantity of pattern data of the characters and figures corresponding to the codes. That is, although the memory capacity can be reduced if the quantity of data is reduced, characters and figures are displayed in the form of rough mosaic images. Thus, the image quality deteriorates. If the quantity of data is enlarged, precise characters and figures can be displayed. However, a large memory is required and, thus, the size of the circuit is enlarged. As a result, an economical disadvantage takes place. Since only patterns stored in the character ROM 24 can be displayed, the characters and figures to be displayed have unsatisfactorily small degree of freedom. If a plurality of characters and figures are enabled to be displayed, a great memory is required.
As described above, the conventional digital image processor requiring a large memory when precise characters and figures are displayed has a problem of structural and economical disadvantages.